From a899bf07c4743b8e916281717b0ff1caab77daba Mon Sep 17 00:00:00 2001 From: "awilliam@xenbuild.aw" Date: Wed, 18 Oct 2006 22:07:06 -0600 Subject: [PATCH] [IA64] Correctly not handle VHPT long format. Signed-off-by: Tristan Gingold --- xen/arch/ia64/vmx/vmx_process.c | 119 ++++++++++++++++++++------------ xen/arch/ia64/vmx/vtlb.c | 8 --- 2 files changed, 73 insertions(+), 54 deletions(-) diff --git a/xen/arch/ia64/vmx/vmx_process.c b/xen/arch/ia64/vmx/vmx_process.c index ad56bcf8b4..1cedd37300 100644 --- a/xen/arch/ia64/vmx/vmx_process.c +++ b/xen/arch/ia64/vmx/vmx_process.c @@ -269,10 +269,12 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs) int type; u64 vhpt_adr, gppa, pteval, rr, itir; ISR misr; + PTA vpta; thash_data_t *data; VCPU *v = current; + vpsr.val = VCPU(v, vpsr); - misr.val=VMX(v,cr_isr); + misr.val = VMX(v,cr_isr); if (vec == 1) type = ISIDE_TLB; @@ -283,7 +285,8 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs) if(is_physical_mode(v)&&(!(vadr<<1>>62))){ if(vec==2){ - if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){ + if (v->domain != dom0 + && __gpfn_is_io(v->domain, (vadr << 1) >> (PAGE_SHIFT + 1))) { emulate_io_inst(v,((vadr<<1)>>1),4); // UC return IA64_FAULT; } @@ -322,41 +325,55 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs) nested_dtlb(v); return IA64_FAULT; } - } else{ - vmx_vcpu_thash(v, vadr, &vhpt_adr); - if(!guest_vhpt_lookup(vhpt_adr, &pteval)){ - if (!(pteval & _PAGE_P)) { - if (vpsr.ic) { - vcpu_set_isr(v, misr.val); - data_page_not_present(v, vadr); - return IA64_FAULT; - } else { - nested_dtlb(v); - return IA64_FAULT; - } - } - else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) { - vcpu_get_rr(v, vadr, &rr); - itir = rr&(RR_RID_MASK | RR_PS_MASK); - thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB); - return IA64_NO_FAULT; - } else if (vpsr.ic) { + } + + vmx_vcpu_get_pta(v, &vpta.val); + if (vpta.vf) { + /* Long format is not yet supported. */ + if (vpsr.ic) { + vcpu_set_isr(v, misr.val); + dtlb_fault(v, vadr); + return IA64_FAULT; + } else { + nested_dtlb(v); + return IA64_FAULT; + } + } + + vmx_vcpu_thash(v, vadr, &vhpt_adr); + if (!guest_vhpt_lookup(vhpt_adr, &pteval)) { + /* VHPT successfully read. */ + if (!(pteval & _PAGE_P)) { + if (vpsr.ic) { vcpu_set_isr(v, misr.val); - dtlb_fault(v, vadr); + data_page_not_present(v, vadr); return IA64_FAULT; - }else{ + } else { nested_dtlb(v); return IA64_FAULT; } + } else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) { + vcpu_get_rr(v, vadr, &rr); + itir = rr & (RR_RID_MASK | RR_PS_MASK); + thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB); + return IA64_NO_FAULT; + } else if (vpsr.ic) { + vcpu_set_isr(v, misr.val); + dtlb_fault(v, vadr); + return IA64_FAULT; }else{ - if(vpsr.ic){ - vcpu_set_isr(v, misr.val); - dvhpt_fault(v, vadr); - return IA64_FAULT; - }else{ - nested_dtlb(v); - return IA64_FAULT; - } + nested_dtlb(v); + return IA64_FAULT; + } + } else { + /* Can't read VHPT. */ + if (vpsr.ic) { + vcpu_set_isr(v, misr.val); + dvhpt_fault(v, vadr); + return IA64_FAULT; + } else { + nested_dtlb(v); + return IA64_FAULT; } } }else if(type == ISIDE_TLB){ @@ -367,24 +384,34 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs) vcpu_set_isr(v, misr.val); alt_itlb(v, vadr); return IA64_FAULT; - } else{ - vmx_vcpu_thash(v, vadr, &vhpt_adr); - if(!guest_vhpt_lookup(vhpt_adr, &pteval)){ - if (pteval & _PAGE_P){ - vcpu_get_rr(v, vadr, &rr); - itir = rr&(RR_RID_MASK | RR_PS_MASK); - thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB); - return IA64_NO_FAULT; - } else { - vcpu_set_isr(v, misr.val); - inst_page_not_present(v, vadr); - return IA64_FAULT; - } - }else{ + } + + vmx_vcpu_get_pta(v, &vpta.val); + if (vpta.vf) { + /* Long format is not yet supported. */ + vcpu_set_isr(v, misr.val); + itlb_fault(v, vadr); + return IA64_FAULT; + } + + + vmx_vcpu_thash(v, vadr, &vhpt_adr); + if (!guest_vhpt_lookup(vhpt_adr, &pteval)) { + /* VHPT successfully read. */ + if (pteval & _PAGE_P) { + vcpu_get_rr(v, vadr, &rr); + itir = rr & (RR_RID_MASK | RR_PS_MASK); + thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB); + return IA64_NO_FAULT; + } else { vcpu_set_isr(v, misr.val); - ivhpt_fault(v, vadr); + inst_page_not_present(v, vadr); return IA64_FAULT; } + } else { + vcpu_set_isr(v, misr.val); + ivhpt_fault(v, vadr); + return IA64_FAULT; } } return IA64_NO_FAULT; diff --git a/xen/arch/ia64/vmx/vtlb.c b/xen/arch/ia64/vmx/vtlb.c index 4fb31a0ec2..2e83358972 100644 --- a/xen/arch/ia64/vmx/vtlb.c +++ b/xen/arch/ia64/vmx/vtlb.c @@ -218,7 +218,6 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte) { u64 ret; thash_data_t * data; - PTA vpta; data = vhpt_lookup(iha); if (data == NULL) { @@ -227,13 +226,6 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte) thash_vhpt_insert(current, data->page_flags, data->itir ,iha); } - /* VHPT long format is not read. */ - vmx_vcpu_get_pta(current, &vpta.val); - if (vpta.vf == 1) { - *pte = 0; - return 0; - } - asm volatile ("rsm psr.ic|psr.i;;" "srlz.d;;" "ld8.s r9=[%1];;" -- 2.30.2